Improvements in semiconductor technology and semiconductor manufacturing processes have resulted in increasingly smaller electronic transistors and highly integrated semiconductor circuits. Typically, a very large number of transistors are integrated into a single multi-function chip. Yet despite continued reduction in the unit transistor power, the power density of unit die area continues to grow rapidly as the demand for high performance and high speed chips increases. This has been particularly true for processors, communication chips and some power chips.
Requiring chips to support high power and high electric current can have significant implications for management of the package structure and interconnection techniques for the electronic packages used to deliver the chips. Typically, a semiconductor circuit package includes a substrate on which the chip is mounted. A conventional form of the substrate is a leadframe, which is frequently made from a copper alloy material, and includes a plane area, or paddle, to support the semiconductor chip. Traditional leadframes include both single layer and multi-layer leadframes. Current high performance leadframes used in semiconductor packaging are typically multi-layer leadframes, and producing these leadframes is generally a complex and expensive process.
Interconnecting the semiconductor chip and the substrate typically involves either solder bumpers or wire bond technology. Wire bond technology is widely used for leadframe-based packages, and a popular material for the wire is pure gold doped with tiny amounts of other doped elements. As chip sizes are reduced, the available bond area and pitch are also made smaller, which may require the use of thinner gold wires as the interconnection media.